(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes to the formation of polysilicon gate MOSFETs.
(2) Background of the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. Most of the ICs produced today utilize the MOSFET (metal oxide silicon field effect transistor) as the basic semiconductive device. MOSFETs are chosen over their bipolar counterparts because they can be easily manufactured and, because they operate at low voltages and currents, they generate less heat thereby making them well suited for high density circuit designs.
The most widely used MOSFET device is the self-aligned polysilicon gate MOSFET which is shown in cross section in FIG. 1. The device 6 is constructed on a monocrystalline silicon wafer 10. A field oxide isolation 12 surrounds an island of active silicon whereupon the device is formed. The main elements of the device are the gate oxide 14, the source/drain regions 22, and the gate electrode 16. Generally, LDD (lightly doped drain) regions 18 are formed through the use of insulative sidewalls 20 to moderate the p/n junctions at the ends of the channel region which develops during operation directly below the gate oxide 14. transition metal silicide regions 24 are formed over the polysilicon gate electrode 16 and source/drain regions 22 to lower the resistivity of the polysilicon gate electrode 16 and subsequently formed source/drain contacts. The LDD 18 and source/drain 22 regions are formed by ion implantation and are self-aligned to the gate electrode. Variations of the MOSFET design are prevalent.
The structure shown in FIG. 1 shows the basic elements of the MOSFET. Often the gate electrode is more complex, consisting of a multilayered structure having a doped polysilicon layer over an undoped layer. In addition a silicide layer is deposited onto the doped layer. When self-aligned source/drain contacts are formed, an additional insulative layer is added over the conductive layers which form the gate electrode. The various layers which form the gate electrode are successively blanket deposited on silicon wafer and then patterned with a photolithographic mask such as photoresist or a hardmask.
As device geometries shrink to achieve higher and higher circuit densities, the thickness of the gate oxide has become extraordinarily thin. In current technologies, gate oxide of less than 100 .ANG. are commonplace and oxide thicknesses of the order of 30 .ANG. are contemplated. This presents a considerable concern in etching the gate electrode stack because the oxide is relied upon to act as an etch stop, preventing attack of the subjacent silicon active regions. The development of improved etching tools such as HDP (high density plasma) ietchers together with improved etchant chemistries have resulted in the achievement of high polysilicon-to-oxide etching selectivities which have, to a degree, permitted the use of thinner gate oxides. However, these improvements are approaching a limitation. Problems of penetration of oxide weak spots are increasingly more prevalent.
This problem is illustrated in the cross section of FIG. 2 wherein the gate stack 16 has been etched to the thin oxide 14 using a photoresist mask 26. Weak or thin spots in the oxide 14 are penetrated by the silicon etch resulting in deep spikes 28 in the subjacent monocrystalline silicon 10. It is expected that the severity of these spiking problems will rapidly increase as gate oxide thicknesses are further reduced. It is apparent that it would be desirable adopt a MOSFET design which would to avoid these problems without sacrificing the desirable operational features of the present structure. The current invention, by using a gate electrode embedded in a trench, provides a MOSFET design for achieving this goal and a method for forming the same.
Other references have described MOSFET designs using trench embedded polysilicon gate structures. Hsu, U.S. Pat. No. 5,576,227 shows a structure wherein a MOSFET gate and gate electrode are formed in a shallow trench wherein the gate oxide and the gate electrode are defined by two back-to-back spacers on of which extends into the trench. The spacer pair provides a robust insulative separator between the gate electrode and the source/drain regions. However, the structure lacks LDD regions. Kwan, et.al., U.S. Pat. No. 5,665,619 shows a DMOS transistor (double diffused MOSFET) formed in a deep trench. A DMOS transistor is a high power device in which current is supplied by two sources through two separate gates to a common drain. The sources and their respective channel regions are located along opposing vertical sides of a trench with the common gate electrode in between and the drain beneath. Matsuda, et.al., U.S. Pat. No. 5,770,514 also shows a vertical channel double diffused FET formed on the sidewalls of a trench.